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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. july 2004 copyright ? intel corporation, 2004 order number: 270909-007 8xc196kb/8xc196kb16 commercial/express chmos microcontroller y 8 kbytes of on-chip rom/otp available y 232 byte register file y register-to-register architecture y 28 interrupt sources/16 vectors y 1.75 m s 16 x 16 multiply (16 mhz) y 3.0 m s 32/16 divide (16 mhz) y powerdown and idle modes y five 8-bit i/o ports y 16-bit watchdog timer y 12 mhz and 16 mhz available y dedicated 15-bit baud rate generator y dynamically configurable 8-bit or 16-bit buswidth y full duplex serial port y high speed i/o subsystem y 16-bit timer y 16-bit up/down counter with capture y pulse-width-modulated output y four 16-bit software timers y 10-bit a/d converter with sample/hold y hold /hlda bus protocol y extended temperature available the 8xc196kb is a 16-bit microcontroller available in three different memory varieties: romless (80c196kb), 8k rom (83c196kb) and 8k otp (one time programmable - 87c196kb). the 8xc196kb is a high perform- ance member of the mcs 96 microcontroller family. the 8xc196kb has the same peripheral set as the 8096bh and has a true superset of the 8096bh instructions. intel's chmos process provides a high perform- ance processor along with low power consumption. to further reduce power requirements, the processor can be placed into idle or powerdown mode. bit, byte, word and some 32-bit operations are available on the 80c196kb. with a 16 mhz oscillator a 16-bit addition takes 0.50 m s, and the instruction times average 0.37 m s to 1.1 m s in typical applications. four high-speed capture inputs are provided to record times when events occur. six high-speed outputs are available for pulse or waveform generation. the high-speed output can also generate four software timers or start an a/d conversion. events can be based on the timer or up/down counter. also provided on-chip are an a/d converter, serial port, watchdog timer and a pulse-width-modulated output signal. the 8xc196kb has a maximum guaranteed frequency of 12 mhz. the 8xc196kb16 has a maximum guaran- teed frequency of 16 mhz. all references to the 80c196kb also refer to the 80c196kb16; 83c196kb, rxxx; 87c196kb and 87c196kb16 unless otherwise noted. the rom device does not have a speed indicator at the end of the device name. instead it has a rom code number. with the commercial (standard) temperature option, operational characteristics are guaranteed over the tem- perature range of 0 cto a 70 c. with the extended temperature range option, operational characteristics are guaranteed over the temperature range of b 40 cto a 85 c. * other brands and names are the property of their respective owners.
8xc196kb/8xc196kb16 270909 1 figure 1. 8xc196kb block diagram 2
8xc196kb/8xc196kb16 proces s information thi s devic e i s manufacture d o n p629. 0 an d 629.1 , a chmo s iii- e process . additiona l proces s an d reli- abilit y informatio n i s availabl e i n the intel ? quality syste m handbook: http://developer.intel.com/design/quality/quality.htm 270909 C 2 note: 1 . e p r om s ar e availabl e a s on e tim e programmable (otp r om ) only. figure 2. the 8xc196kb nomenclature table 1. thermal characteristics package ja jc type plc c 35 c/ w 13 c/w qf p 70 c/ w 4 c/w al l therma l impedanc e dat a i s approximat e fo r stati c air condition s a t 1 w o f powe r dissipation . value s wil l change dependin g o n operatio n condition s an d application . see th e intel packagin g handbook (orde r numbe r 240800 ) fo r a descriptio n o f intel s therma l impedanc e tes t methodology. table 2. 8xc196kb memory map description address externa l memor y o r i/ o 04000h interna l rom/ e p r o m o r externa l memor y (determine d b y ea ) 2080h reserved . mus t contai n ffh. (not e 5) 2040h uppe r interrup t vector s 203fh 2030h rom/ e p r o m securit y ke y 202fh 2020h reserved . mus t contai n ffh. (not e 5) 201ah reserved . mus t contai n 20h. (not e 5) cc b 2018h reserved . mus t contai n ffh. (not e 5) 2014h lowe r interrup t vector s 2013h 2000h port 3 an d por t 4 1fffh 1ffeh externa l memor y 1ffdh 0100h 23 2 byte s registe r ra m (not e 1 ) 00ffh 0018h cp u sfr s (note s 1 , 3 ) 0017h 0000h notes: 1 . cod e execute d i n location s 0000 h t o 00ff h wil l be force d external. 2 . reserve d memor y location s mus t contai n 0ff h unless noted. 3 . reserve d sf r bi t location s mus t contai n 0. 4 . refe r t o 8xc196k b quic k referenc e fo r sf r descrip- tions. 5. warning: reserve d memor y location s mus t no t be writte n o r read . th e content s and/o r functio n o f thes e lo- cation s ma y chang e wit h futur e revision s o f th e device. therefore, a progra m tha t relie s o n on e o r mor e o f these location s ma y no t functio n properly. 3 207fh 201fh 2019h 2017h 0ffffh 3fffh
8xc196kb/8xc196kb16 270909 C 3 figure 3. 68-pin package (plcc top view) note: th e abov e pi n ou t diagra m applie s t o th e ot p (87c196kb ) device . th e ot p devic e use s al l o f th e programmin g pin s shown above . th e ro m (83c196kb ) devic e onl y use s programmin g pins : ainc , pale , pmode.n , an d prog . th e romless (80c196kb ) doesn t us e an y o f th e programmin g pins. 4
8xc196kb/8xc196kb16 270909 C 4 note: n.c . mean s n o connec t (d o no t connec t thes e pins). figure 4. 80-pin qfp package note: th e abov e pi n ou t diagra m applie s t o th e ot p (87c196kb ) device . th e ot p devic e use s al l o f th e programmin g pin s shown above . th e ro m (83c196kb ) devic e onl y use s programmin g pins : ainc , pale , pmode.n , an d prog . th e romless (80c196kb ) doesn t us e an y o f th e programmin g pins. 5
8xc196kb/8xc196kb16 pin descriptions symbol name and function v cc main supply voltage (5v). v ss digital circuit ground (0v). there are multiple v ss pins, all of them must be connected. v ref reference voltage for the a/d converter (5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . connect v ss and angnd at chip to avoid noise problems. v pp programming voltage. also timing pin for the return from power down circuit. xtal1 input of the oscillator inverter and of the internal clock generator. xtal2 output of the oscillator inverter. clkout output of the internal clock generator. the frequency of clkout is (/2 the oscillator frequency. it has a 50% duty cycle. reset reset input to and open-drain output from the chip. input low for at least 4 state times to reset the chip. the subsequent low-to-high transition re-synchronizes clkout and commences a 10-state-time reset sequence. buswidth input for buswidth selection. if ccr bit 1 is a one, this pin selects the bus width for the bus cycle in progress. if buswidth is a 1, a 16-bit bus cycle occurs. if buswidth i sa0an 8-bit cycle occurs. if ccr bit 1 is a 0, the bus is always an 8-bit bus. nmi a positive transition causes a vector through 203eh. inst output high during an external memory read indicates the read is an instruction fetch and output low indicates a data fetch. inst is valid throughout the bus cycle. inst is activated only during external memory accesses. ea input for memory select (external access). ea equal to a ttl-high causes memory accesses to locations 2000h through 3fffh to be directed to on-chip rom/otpr om. ea equal to a ttl-low causes accesses to these locations to be directed to off-chip memory. ale/adv address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when the pin is adv , it goes inactive high at the end of the bus cycle. ale/adv is activated only during external memory accesses. rd read signal output to external memory. rd is activated only during external memory reads. wr /wrl write and write low output to external memory, as selected by the ccr. wr will go low for every external write, while wrl will go low only for external writes where an even byte is being written. wr /wrl is activated only during external memory writes. bhe /wrh bus high enable or write high output to external memory, as selected by the ccr. bhe will go low for external writes to the high byte of the data bus. wrh will go low for external writes where an odd byte is being addressed. bhe /wrh is activated only during external memory writes. ready ready input to lengthen external memory cycles. if the pin is low prior to the falling edge of clkout, the memory controller goes into a wait mode until the next positive transition in clkout occurs with ready high. when the external memory is not being used, ready has no effect. internal control of the number of wait states inserted into a bus cycle (held not ready) is available in the ccr. hsi inputs to high speed input unit. four hsi pins are available: hsi.0, hsi.1, hsi.2 and hsi.3. two of them (hsi.2 and hsi.3) are shared with the hso unit. hso outputs from high speed output unit. six hso pins are available: hso.0, hso.1, hso.2, hso.3, hso.4 and hso.5. two of them (hso.4 and hso.5) are shared with the hsi unit. 6
8xc196kb/8xc196kb16 pin descriptions (continued) symbol name and function port 0 8-bit high impedance input-only port. three pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. port 1 8-bit quasi-bidirectional i/o port. these pins are shared with hold , hlda and breq . port 2 8-bit multi-functional port. all of its pins are shared with other functions in the 87c196kb. pins p2.6 and p2.7 are quasi-bidirectional. ports 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus, which has strong internal pullups. hold bus hold input requesting control of the bus. enabled by setting wsr.7. hlda bus hold acknowledge output indicating release of the bus. enabled by setting wsr.7. breq bus request output activated when the bus controller has a pending external memory cycle. enabled by setting wsr.7. txd the txd pin is used for serial port transmission in modes 1, 2 and 3. in mode 0 the pin is used as the serial clock output. rxd serial port receive pin used for serial port reception. in mode 0 the pin functions as input or output data. extint a rising edge on the extint pin will generate an external interrupt. t2clk the t2clk pin is the timer2 clock input or the serial port baud rate generator input. t2rst a rising edge on the t2rst pin will reset timer2. pwm the pulse width modulator output. t2up-dn the t2updn pin controls the direction of timer2 as an up or down counter. t2capture a rising edge on p2.7 will capture the value of timer2 in the t2capture register. pmode programming mode select. determines the eprom programming algorithm that is performed. pmode is sampled after a chip reset and should be static while the part is operating. sid slave id number. used to assign each slave a pin of port 3 or 4 to use for passing programming verification acknowledgement. pale programming ale input. accepted by the 87c196kb when it is in slave programming mode. used to indicate that ports 3 and 4 contain a command/address. prog programming. falling edge indicates valid data on pbus and the beginning of programming. rising edge indicates end of programming. pact programming active. used in the auto programming mode to indicate when programming activity is complete. pval program valid. this signal indicates the success or failure of programming in the auto programming mode. a zero indicates successful programming. pver program verification. used in slave programming and auto clb programming modes. signal is low after rising edge of prog if the programming was not successful. ainc auto increment. active low signal indicates that the auto increment mode is enabled. auto increment will allow reading or writing of sequential eprom locations without address transactions across the pbus for each read or write. ports 3 address/command/data bus. used to pass commands, addresses, and data to and from slave mode 87c196kbs. used by chips in auto programming mode to pass command, and 4 addresses and data to slaves. also used in the auto programming mode as a regular (programming system bus to access external memory. should have pullups to v cc when used in slave mode) programming mode. 7
8xc196kb/8xc196kb16 electrical characteristics absolute maximum ratings * ambient temperature under bias................................. b 55 cto a 125 c storage temperature................... . b 65 ct o a 150 c voltage on any pin to v ss ................ b 0.5v to a 7.0v power dissipation (1) .......................... 1.5w note: 1. power dissipation is based on package heat transfer lim- itations, not device power consumption. notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions (all characteristics in this data sheet apply to these operating conditions unless otherwise noted.) symbol description min max units t a ambient temperature under bias 0 a 70 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v f osc oscillator frequency 12 mhz 3.5 12 mhz f osc oscillator frequency 16 mhz 3.5 16 mhz note: angnd and v ss should be nominally at the same potential. dc characteristics symbol description min max units test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage (all pins except 0.2 v cc a 0.9 v cc a 0.5 v xtal1 and reset) v ih1 input high voltage on xtal 1 0.7 v cc v cc a 0.5 v v ih2 input high voltage on reset 2.6 v cc a 0.5 v v ol output low voltage 0.3 v i ol e 200 m a 0.45 v i ol e 3.2 ma 1.5 v i ol e 7ma v oh output high voltage v cc b 0.3 v i oh eb 200 m a (standard outputs) (2) v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7ma v oh1 output high voltage v cc b 0.3 v i oh eb 10 m a (quasi-bidirectional outputs) (1) v cc b 0.7 v i oh eb 30 m a v cc b 1.5 v i oh eb 60 m a i li input leakage current g 10 m a0 k v in k v cc b 0.3v (std. inputs) (3) i li1 input leakage current (port 0) a 3 m a0 k v in k v ref i tl 1 to 0 transition current b 800 m av in e 2.0v (qbd pins) (1) i il logical 0 input current (qbd pins) (1) b 50 m av in e 0.45v 8
8xc196kb/8xc196kb16 dc characteristics (continued) symbol description min typ (7) max units t est conditions i il1 logical 0 input current in reset b 850 m av in e 0.45v bhe ,wr , p2.0 i il2 logical 0 input current in reset b 7mav in e 0.45v ale, rd , inst i ih1 logical 1 input current 100 m av in e 2.0v on nmi pin hyst. hysteresis on reset pin 300 mv i cc active mode current in reset 50 60 ma xtal1 e 16 mhz i ref a/d converter reference current 2 5 ma v cc e v pp e v ref e 5.5v i idle idle mode current 10 25 ma i pd powerdown mode current 5 30 m av cc e v pp e v ref e 5.5v r rst reset pullup resistor 6k 50k x c s pin capacitance (any pin to v ss )1 0 p f f test e 1.0 mhz notes: (notes apply to all specifications) 1. qbd (quasi-bidirectional) pins include port 1, p2.6 and p2.7. 2. standard outputs include ad015, rd ,wr , ale, bhe , inst, hso pins, pwm/p2.5, clkout, reset, ports 3 and 4, txd/p2.0 and rxd (in serial mode 0). the v oh specification is not valid for reset. ports 3 and 4 are open-drain outputs. 3. standard inputs include hsi pins, ea , ready, buswidth, nmi, rxd/p2.1, extint/p2.2, t2clk/p2.3 and t2rst/ p2.4. 4. maximum current per pin must be externally limited to the following values if v ol is held above 0.45v or v oh is held below v cc b 0.7v: i ol on output pins: 10 ma i oh on quasi-bidirectional pins: self limiting i oh on standard output pins: 10 ma 5. maximum current per bus pin (data and control) during normal operation is g 3.2 ma. 6. during normal (non-transient) conditions the following total current limits apply: port 1, p2.6 i ol :29ma i oh is self limiting hso, p2.0, rxd, reset i ol :29ma i oh :26ma p2.5, p2.7, wr , bhe i ol :13ma i oh :11ma ad0ad15 i ol :52ma i oh :52ma rd , ale, instclkout i ol :13ma i oh :13ma 7. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and v ref e v cc e 5v. i cc max e 3.88 c freq a 8.43 270909 5 i idle max e 1.65 c freq a 2.2 figure 6. i cc and i idle vs frequency 9
8xc196kb/8xc196kb16 ac characteristics test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 12/16 mhz the system must meet these specifications to work with the 87c196kb: symbol description min max units notes t avyv address valid to ready setup 2 t osc b 75 ns t ylyh nonready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (note 1) t llyx ready hold after ale low t osc b 15 2 t osc b 40 ns (note 1) t avgv address valid to buswidth setup 2 t osc b 75 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns (note 2) t rldv rd active to input data valid t osc b 23 ns (note 2) t cldv clkout low to input data valid t osc b 50 ns t rhdz end of rd to input data float t osc b 20 ns t rxdx data hold after rd inactive 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. when using wait states, add 2 t osc c n where n e number of wait states. 10
8xc196kb/8xc196kb16 ac characteristics (continued) test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 12/16 mhz the 87c196kb will meet these specifications: symbol description min max units notes f xtal frequency on xtal1 12 mhz 3.5 12.0 mhz (note 2) f xtal frequency on xtal1 16 mhz 3.5 16.0 mhz (note 2) t osc 1/f xtal 12 mhz 83.3 286 ns t osc 1/f xtal 16 mhz 62.5 286 ns t xhch xtal1 high to clkout high or low a 20 a 110 ns t clcl clkout cycle time 2 t osc ns t chcl clkout high period t osc b 10 t osc a 10 ns t cllh clkout falling edge to ale rising b 10 a 10 ns t llch ale falling edge to clkout rising b 15 a 15 ns t lhlh ale cycle time 4 t osc ns (note 3) t lhll ale high period t osc b 10 t osc a 10 ns t avll address setup to ale falling edge t osc b 20 ns t llax address hold after ale falling edge t osc b 40 ns t llrl ale falling edge to rd falling edge t osc b 35 ns t rlcl rd low to clkout falling edge a 4 a 25 ns t rlrh rd low period t osc b 5t osc a 25 ns (note 3) t rhlh rd rising edge to ale rising edge t osc t osc a 25 ns (note 1) t rlaz rd low to address float a 5ns t llwl ale falling edge to wr falling edge t osc b 10 ns t clwl clkout low to wr falling edge 0 a 25 ns t qvwh data stable to wr rising edge t osc b 23 ns (note 3) t chwh clkout high to wr rising edge b 5 a 15 ns t wlwh wr low period t osc b 15 t osc a 5 ns (note 3) t whqx data hold after wr rising edge t osc b 15 ns t whlh wr rising edge to ale rising edge t osc b 15 t osc a 10 ns (note 1) t whbx bhe , inst hold after wr rising edge t osc b 15 ns t rhbx bhe , inst hold after rd rising edge t osc b 10 ns t whax ad815 hold after wr rising edge t osc b 30 ns t rhax ad815 hold after rd rising edge t osc b 25 ns notes: 1. assuming back-to-back bus cycles. 2. testing performed at 3.5 mhz, however, the device is static by design and will typically operate below 1 hz. 3. when using wait states, all 2 t osc a n where n e number of wait states. 11
8xc196kb/8xc196kb16 system bus timings 270909 6 12
8xc196kb/8xc196kb16 ready timings (one wait state) 270909 7 buswidth bus timings 270909 8 13
8xc196kb/8xc196kb16 hold /hlda timings symbol description min max units notes t hvch hold setup 55 ns (note 1) t clhal clkout low to hlda low 15 ns t clbrl clkout low to breq low 15 ns t halaz hlda low to address float 10 ns t halbz hlda low to bhe , inst, rd ,wr float 10 ns t clhah clkout low to hlda high b 15 15 ns t clbrh clkout low to breq high b 15 15 ns t hahax hlda high to address no longer float b 15 ns t hahav hlda high to address valid 0 ns t hahbx hlda high to bhe , inst, rd ,wr no longer float b 20 ns t hahbv hlda high to bhe , inst, rd ,wr valid 0 ns t cllh clkout low to ale high b 515 ns note: 1. to guarantee recognition at next clock. maximum hold latency bus cycle type latency internal access 1.5 states 16-bit external execution 2.5 states 8-bit external 4.5 states 270909 9 14
8xc196kb/8xc196kb16 external clock drive symbol parameter min max units 1/t xlxl oscillator frequency 12 mhz 3.5 12.0 mhz 1/t xlxl oscillator frequency 16 mhz 3.5 16 mhz t xlxl oscillator period 12 mhz 83.3 286 ns t xlxl oscillator period 16 mhz 62.5 286 ns t xhxx high time 21.25 ns t xlxx low time 21.25 ns t xlxh rise time 10 ns t xhxl fall time 10 ns external clock drive waveforms 270909 10 an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts-up. this is due to interaction between the amplifier and its feedback capacitance. once the external signal meets the v il and v ih specifications, the capacitance will not exceed 20 pf. external crystal connections 270909 11 note: keep oscillator components close to chip and use short, direct traces to xtal1, xtal2 and v ss . when using crystals, c1 e 20 pf, c2 e 20 pf. when using ceramic resonators, consult manufacturer for recom- mended circuitry. external clock connections 270909 12 * required if open-collector ttl driver used not needed if cmos driver is used. ac testing input, output waveforms 270909 13 ac testing inputs are driven at 2.4v for a logic ``1'' and 0.45v for a logic ``0'' timing measurements are made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. float waveforms 270909 14 for timing purposes a port pin is no longer floating when a 200 mv change from load voltage occurs and begins to float when a 200 mv change from the loaded v oh /v ol level occurs; i ol /i oh e g 15 ma. 15
8xc196kb/8xc196kb16 explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: signals: h - high l - low v - valid x - no longer valid z - floating a - address b - bhe br - breq c - clkout d - data in g - buswidth h - hold ha - hlda l - ale/adv q - data out r-rd w-wr /wrh /wrl x - xtal1 y - ready ac characteristics-serial port-shift register mode serial port timing-shift register mode (mode 0 ) symbol parameter min max units t xlxl serial port clock period (brr t 8002h) 6 t osc ns t xlxh serial port clock falling edge to rising edge (brr t 8002h) 4 t osc b 50 4 t osc a 50 ns t xlxl serial port clock period (brr e 8001h) 4 t osc ns t xlxh serial port clock falling edge to rising edge (brr e 8001h) 2 t osc b 50 2 t osc a 50 ns t qvxh output data setup to clock rising edge 2 t osc b 50 ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid after clock rising edge 2 t osc a 50 ns t dvxh input data setup to clock rising edge t osc a 50 ns t xhdx input data hold after clock rising edge 0 ns t xhqz last clock rising to output float 2 t osc ns waveform-serial port-shift register mode serial port waveform-shift register mode (mode 0) 270909 18 16
8xc196kb/8xc196kb16 10-bit a/d characteristics at a clock speed of 6 mhz or less, the clock prescal- er should be disabled. this is accomplished by set- ting ioc2.4 e 1. at higher frequencies (greater than 6 mhz) the clock prescaler should be enabled (ioc2.4 e 0) to allow the comparator to settle. the table below shows two different clock speeds and their corresponding a/d conversion and sample times. state times are calculated as follows: state time e 2 xtal1 the converter is ratiometric, so the absolute accura- cy is directly dependent on the accuracy and stability of v ref .v ref must be close to v cc since it supplies both the resistor ladder and the digital section of the converter. see the mcs-96 a/d converter quick reference for definition of a/d terms. example sample and conversion times sample time conversion conversion a/d clock clock speed sample time at clock time time at prescaler (mhz) (states) speed (states) clock speed ( m s) ( m s) ioc2.4 e 0 x on 16 15 1.875 156.5 19.6 ioc2.4 e 1 x off 6 8 2.667 89.5 29.8 a/d converter specifications parameter typical(1) minimum maximum units * notes resolution 1024 1024 levels 10 10 bits absolute error 0 g 3 lsbs full scale error 0.25 g 0.50 lsbs zero offset error 0.25 g 0.50 lsbs non-linearity error 1.5 g 2.5 0 g 3 lsbs differential non-linearity error l b 1 a 2 lsbs channel-to-channel matching g 0.1 0 g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.009 lsb/ c full scale 0.009 lsb/ c differential non-linearity 0.009 lsb/ c off isolation b 60 db 2, 3 feedthrough b 60 db 2 v cc power supply rejection b 60 db 2 input series resistance 750 1.2k x 4 dc input leakage 0 g 3.0 m a sampling capacitor 3 pf notes: * an ``lsb'', as used here, has a value of approximately 5 mv. 1. typical values are expected for most devices at 25 c. 2. dc to 100 khz. 3. multiplexer break-before-make guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 17
8xc196kb/8xc196kb16 otprom specifications otprom programming operating conditions symbol parameter min max units t a ambient temperature during programming 20 30 c v cc ,v pd ,v ref (1) supply voltages during programming 4.5 5.5 v v ea programming mode supply voltage 12.50 13.0 v (2) v pp eprom programming supply voltage 12.50 13.0 v (2) v ss , angnd (3) digital and analog ground 0 0 v f osc oscillator frequency 12 mhz 6.0 12.0 mhz f osc oscillator frequency 16 mhz 6.0 16.0 mhz notes: 1. v cc ,v pd and v ref should nominally be at the same voltage during programming. 2. v ea and v pp must never exceed the maximum voltage for any amount of time or the device may be damaged. 3. v ss and angnd should nominally be at the same voltage (0v) during programming. ac otprom programming characteristics symbol description min max units t shll reset high to first pale low 1100 t osc t lllh pale pulse width 40 t osc t avll address setup time 0 t osc t llax address hold time 50 t osc t llvl pale low to pver low 60 t osc t pldv prog low to word dump valid 50 t osc t phdx word dump data hold 50 t osc t dvpl data setup time 0 t osc t pldx data hold time 50 t osc t plph prog pulse width 40 t osc t phll prog high to next pale low 120 t osc t lhpl pale high to prog low 220 t osc t phpl prog high to next prog low 120 t osc t phil prog high to ainc low 0 t osc t ilih ainc pulse width 40 t osc t ilvh pver hold after ainc low 50 t osc t ilpl ainc low to prog low 170 t osc t phvl prog high to pver low 90 t osc 18
8xc196kb/8xc196kb16 dc otprom programming characteristics symbol description min max units i pp v pp supply current (when programming) 100 ma note: do not apply v pp until v cc is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. otprom programming waveforms slave programming mode data program mode with single program pulse 270909 15 slave programming mode in word dump or data verify mode with auto increment 270909 16 19
8xc196kb/8xc196kb16 slave programming mode timing in data program mode with repeated prog pulse and auto increment 270909 17 20
8xc196kb/8xc196kb16 functional deviations device s marke d wit h a n e , f o r g hav e the followin g errata. 1 . missed interrupt on p0.7, extint interrupt s occurrin g o n p0. 7 coul d b e misse d since th e int_pen d extin t bi t ma y no t b e set . see techbi t mc0893. 2 . hsi_ mod e divide-by-eight revisio n history thi s dat a shee t (270909-006 ) i s vali d fo r devices wit h a n e , f o r g a t th e en d o f th e to p side trackin g number . dat a sheet s ar e change d a s new devic e informatio n become s available . verif y with you r loca l inte l sale s offic e tha t yo u hav e th e latest versio n befor e finalizin g a desig n o r orderin g devic- es. th e followin g difference s exis t betwee n data shee t 270909-006 an d 270909-005. 1 . remove d wor d addressabl e only fro m por t 3 an d 4 i n tabl e 2. 2 . remove d icc1 , activ e mod e curren t a t 3. 5 mhz. thi s specificatio n i s no t longe r required. 3 . remove d tlly v an d tllg v fro m wavefor m dia- grams. 4 . th e hs i errat a an d cmp l wit h r 0 wer e removed a s thi s i s no w considere d norma l operation. 5 . th e hsi_ mod e divide-by-eigh t errat a wa s add- e d t o th e know n errat a section. th e followin g difference s exis t betwee n thi s data shee t (270909-005 ) an d (270909-004). 1 . i tl ma x was C 650 a (270909-004) . no w i tl ma x is C 800 a (270909-005). 2 . i il2 wa s name d i il1 (270909-004) . no w i il2 is correctl y name d (270909-005). 3 . i il1 wa s omitte d (270909-004) . i il1 ma x was added . i il1 ma x is C 850 a (270909-005). 4 . t llyv an d t llgv (270909-004 ) wer e removed. thes e timing s ar e no t require d i n high-spee d sys- te m designs. 5 . a n errat a wa s adde d t o th e know n errat a section. ther e is a possibilit y t o mis s a n externa l interrupt o n p0. 7 extint. th e followin g difference s exis t betwee n thi s data shee t (270909-004 ) an d (270909-003). 1 . th e ro m (80c196kb) , an d romless (83c196kb ) wer e combine d wit h thi s dat a sheet resultin g i n n o specificatio n differences. 2 . th e descriptio n o f th e prescala r bi t fo r th e a/d ha s bee n enhanced. 3 . t hahbv mi n was C 1 5 n s (270909-003) . now t hahbv mi n is C 2 0 n s (270909-004). 4 . t xhqz ma x was 1 tos c (270909-003) . now t xhqz ma x is 2 tos c (270909-004) . thi s should hav e n o impac t o n design s usin g synchronous seria l mod e 0. 5 . th e chang e indicator s fo r th e 80c196k b are e , f an d g . previousl y ther e wa s onl y one chang e indicato r e . th e chang e indicato r is use d fo r trackin g purposes . th e chang e indicator i s th e las t characte r i n th e fp o number . th e fpo numbe r i s th e secon d lin e o n th e to p sid e o f the device. 21 th e followin g difference s exis t betwee n thi s data shee t (270909-007 ) an d (270909-006). 1 . package prefix variables have changed. these variables are now indicated by x.
8xc196kb/8xc196kb16 the following differences exist between (-003) and version (-002). 1. the 12 mhz and 16 mhz devices were com- bined in this data sheet. the 87c196kb 12 mhz only data sheet (272035-001) is now obsolete. 2. changes were made to the format of the data sheet and the sfr descriptions were removed. 3. the -002 version of this data sheet was valid for devices marked with a ``b'' or a ``d'' at the end of the top side tracking number. 4. the oscillator errata was removed. 5. an errata was not documented in the -002 data sheet for devices marked with a ``b'' or a ``d''. this is the divide during hold/ready er- rata. when hold or ready is active and div/ divb is the last instruction in the queue, the di- vide result may be incorrect. 6. t xch was changed from min e 40 ns to min e 20 ns. 7. t rlcl was changed from min e 5nstomin e 4 ns. 9. i il1 was changed from max eb 6matomax e b 7 ma. 10. t hahbv was changed from min eb 10 ns to min eb 15 ns. differences between the -002 and -001 data sheets. 1. the -001 version of this data sheet was valid for devices marked with a ``c'' at the end of the top side tracking number. 2. added 64l sdip and 80l qfp packages. 3. added iih1. 4. changed t chwh min from b 10 ns to b 5 ns. 5. changed t chwh max from a 10 ns to a 15 ns. 6. changed t wlwh min from t osc b 20 ns to t osc b 15 ns. 7. changed t whqx min from t osc b 10 ns to t osc b 15 ns. 8. changed t whlh min from t osc b 10 ns to t osc b 15 ns. 9. changed t whlh max from t osc a 15 ns to t osc a 10 ns. 10. changed t whbx min from t osc b 10 ns to t osc b 15 ns. 11. changed t hvch min from 85 ns to 55 ns. 12. remove t hvch max. 13. changed t clhal min from b 10 ns to b 15 ns. 14. changed t clhal max from 20 ns to 15 ns. 15. changed t clbrl min from b 10 ns to b 15 ns. 16. changed t clbrl max from 20 ns to 15 ns. 17. changed t hahax min from b 10 ns to b 15 ns. 18. added hsi description to functional deviations. 19. added oscillator description to functional devi- ations. 22

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